Physical implementation workload efficiency improvement

EDA workloads on both cloud and on-premises require an understanding of the jobs on the host for the best turnaround time and cost efficiency. A lot of EDA jobs are launched with over demanded compute resources than necessary. They often fail if launched with resources less than what is required, th...

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Main Author: Hasan, Tarique
Other Authors: Matemaattis-luonnontieteellinen tiedekunta, Faculty of Sciences, Fysiikan laitos, Department of Physics, Jyväskylän yliopisto, University of Jyväskylä
Format: Master's thesis
Language:eng
Published: 2024
Subjects:
Online Access: https://jyx.jyu.fi/handle/123456789/97355
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author Hasan, Tarique
author2 Matemaattis-luonnontieteellinen tiedekunta Faculty of Sciences Fysiikan laitos Department of Physics Jyväskylän yliopisto University of Jyväskylä
author_facet Hasan, Tarique Matemaattis-luonnontieteellinen tiedekunta Faculty of Sciences Fysiikan laitos Department of Physics Jyväskylän yliopisto University of Jyväskylä Hasan, Tarique Matemaattis-luonnontieteellinen tiedekunta Faculty of Sciences Fysiikan laitos Department of Physics Jyväskylän yliopisto University of Jyväskylä
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description EDA workloads on both cloud and on-premises require an understanding of the jobs on the host for the best turnaround time and cost efficiency. A lot of EDA jobs are launched with over demanded compute resources than necessary. They often fail if launched with resources less than what is required, thus increasing turnaround time. It is important to have prior knowledge of resource requirements according to design size and workload nature. This work explores synthesis, floorplan, clock tree synthesis, placement, and routing jobs for a small and bigger Arm CPU core design on compute clusters within the Arm’s existing flow. The jobs dependency in terms of runtime and maximum memory utilization on multi-core jobs are investigated on different AMD and Intel machines on AWS cloud servers. It is found that a small design size does not benefit from parallelism. On the other hand, a bigger design has significantly reduced runtime for the implementation jobs when launched with multi-threaded CPUs. This work provides Arm with a method to extract information on EDA jobs with their flow and a schema that can be used for machine learning models to predict and build optimum job configuration
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spellingShingle Hasan, Tarique Physical implementation workload efficiency improvement Elektroniikka Electronics 4022
title Physical implementation workload efficiency improvement
title_full Physical implementation workload efficiency improvement
title_fullStr Physical implementation workload efficiency improvement Physical implementation workload efficiency improvement
title_full_unstemmed Physical implementation workload efficiency improvement Physical implementation workload efficiency improvement
title_short Physical implementation workload efficiency improvement
title_sort physical implementation workload efficiency improvement
title_txtP Physical implementation workload efficiency improvement
topic Elektroniikka Electronics 4022
topic_facet 4022 Electronics Elektroniikka
url https://jyx.jyu.fi/handle/123456789/97355 http://www.urn.fi/URN:NBN:fi:jyu-202410096224
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