| Summary: | Electronic devices are sensitive to single event effects due to one ionizing particle creating a temporary voltage pulse in a transistor of a logic cell. This pulse is called a Single Event Transient. When this pulse is captured in a flip-flop or latch, wrong data can be retained and propagated, which is called a Single Event Upset.
This thesis proposes a circuit level method of detecting the occurrence of a Single Event Effect inside flip-flops, which can be reported to a central processing unit or a dedicated mitigation system. This work builds further on the principle of a double sampling flip-flop, where one main flip-flop captures the data at the positive clock edge, and a separate shadow flip-flop
captures the data on a delayed clock edge. The main and delayed signals are compared by an exclusive or gate, after which this signal is latched to synchronize it with the sequential elements. When both the main output signal and the delayed output signal are the same, no temporary change in the data has occurred around the capturing clock edges of the flip-flops. But when the two signals differ, a transient or upset could have occurred, which needs to be reported.
The thesis presents a double sampling flip-flop design working up to 250MHz in UMC 180 nm technology. The design is synthesized, placed and routed in a layout with a clock tree appropriate for the design. It is shown that the design is functional and can be used as a replacement for a single flip-flop.
The groundwork is laid for a demonstrator chip with a shift register, where every standard cell flip-flop is replaced with the double sample flip-flop design during synthesis. All the Single Event Effects error signals originating from a section of double
sampling flip-flops can be compressed through an OR-tree to maintain a single error signal for that section.
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