Study of a Phase Locked Loop based Clock and Data Recovery circuit for 2.5 Gbps data-rate

Study of a Phase Locked Loop based Clock and Data Recovery circuit for 2.5 Gbps data-rate

Phase Locked Loop (PLL)-based Clock and Data Recovery (CDR) circuits play a big role in communication systems for High-Energy Physics (HEP) since are used to generate a high-quality clock signal that maintains synchronicity between the electronic systems. The CDR topology proposed in this thesis can...

Täydet tiedot

Bibliografiset tiedot
Päätekijä: Marinaci, Stefano
Muut tekijät: Matemaattis-luonnontieteellinen tiedekunta, Faculty of Sciences, Fysiikan laitos, Department of Physics, Jyväskylän yliopisto, University of Jyväskylä
Aineistotyyppi: Pro gradu
Kieli:eng
Julkaistu: 2023
Aiheet:
PLL-based CDR
High-speed Link communication systems
low-noise PLL
Elektroniikka
Electronics
4022
Linkit: https://jyx.jyu.fi/handle/123456789/89109

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