Carbon nanotube memory devices with high-κ gate dielectrics

In this thesis the memory effect and negative differential resistance (NDR) rising from the hysteresis present in carbon nanotube field-effect transistors (CNT-FETs) with high-κ gate dielectrics is discussed. A high-yield fabrication method is devel- oped where Hf-based gate dielectrics are used t...

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Bibliographic Details
Main Author: Rinkiö, Marcus
Other Authors: Faculty of Mathematics and Science, Matemaattis-luonnontieteellinen tiedekunta, University of Jyväskylä, Jyväskylän yliopisto
Format: Doctoral dissertation
Language:eng
Published: 2009
Online Access: https://jyx.jyu.fi/handle/123456789/80377
Description
Summary:In this thesis the memory effect and negative differential resistance (NDR) rising from the hysteresis present in carbon nanotube field-effect transistors (CNT-FETs) with high-κ gate dielectrics is discussed. A high-yield fabrication method is devel- oped where Hf-based gate dielectrics are used to control the memory effect by de- signing the gate dielectric in nm-thin layers. The first CNT-FETs with consistent and narrow distribution memory effects in their transfer characteristics are achieved, by using atomic layer depositions of HfO2 and TiO2 in a triple-layer configuration. The effect of humidity on the hysteresis of the triple-layer gate dielectric is found to be smaller than in CNT-FETs having the more common SiO2 gate dielectric. As a figure of merit, a 100 ns Write/Erase speed is achieved with CNT-FET memory elements having HfO2 as a gate and passivation dielectric. This speed is high enough to compete with state of the art commercial Flash memories. Also the endurance of the memory elements is shown to exceed 104 cycles. A model where the hafnium oxide has defect states situated above, but close in energy to, the band gap of the CNT is discussed. The fast and effective charging and discharging of the defects is shown to be a likely explanation to the 100 ns operation speed, largely exceeding the CNT-FET memory speeds of 10 ms observed earlier. By patterning the triple-layer high-κ gate oxide, quantum dots can be induced into the channel of CNT-FETs. This in turn is used to attain controllable and gate- tunable NDR in these devices. The method is fully scalable and opens up a new avenue for electronic nanoscale devices using NDR in their operation, e.g. nanoscale amplifiers, fast switching elements and high-frequency oscillators operating in the THz domain. All the above findings indicate strong charge trapping in the Hf-based gate dielectrics, which can be utilized in many ways by carefully designing the gate dielectric to suit the application.