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University of Jyväskylä
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High-speed Link communication systems
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Study of a Phase Locked Loop based Clock and Data Recovery circuit for 2.5 Gbps data-rate
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Marinaci, Stefano
Published 2023
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Master's thesis
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High-speed Link communication systems
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PLL-based CDR
low-noise PLL
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Matemaattis-luonnontieteellinen tiedekunta
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electronic circuits
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locks
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