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[{"key": "dc.contributor.advisor", "value": "Leroux, Paul", "language": "", "element": "contributor", "qualifier": "advisor", "schema": "dc"}, {"key": "dc.contributor.advisor", "value": "Le Tual, St\u00e9phane", "language": "", "element": "contributor", "qualifier": "advisor", "schema": "dc"}, {"key": "dc.contributor.author", "value": "Zeeshan, Muhammad", "language": "", "element": "contributor", "qualifier": "author", "schema": "dc"}, {"key": "dc.date.accessioned", "value": "2024-09-25T06:21:55Z", "language": null, "element": "date", "qualifier": "accessioned", "schema": "dc"}, {"key": "dc.date.available", "value": "2024-09-25T06:21:55Z", "language": null, "element": "date", "qualifier": "available", "schema": "dc"}, {"key": "dc.date.issued", "value": "2024", "language": "", "element": "date", "qualifier": "issued", "schema": "dc"}, {"key": "dc.identifier.uri", "value": "https://jyx.jyu.fi/handle/123456789/97200", "language": null, "element": "identifier", "qualifier": "uri", "schema": "dc"}, {"key": "dc.description.abstract", "value": "Several ADC architectures are found to exist such as Successive Approximation Register, \npipeline, sigma-delta, flash etc. The choice of these architectures depends on the\nrequired sampling frequency and resolution of the application. ADCs are known to be \nan essential interface between the analog world and digital computer data. Due to this \nkey function, ADC circuits have been thoroughly studied for over 4 decades, addressing \nnumerous associated challenges. However, a new type of ADCs has recently emerged, \ncapturing significant attention. These are high-speed time-interleaved ADCs (TI ADCs), \ntypically ranging from 1 GS/s to over 50 GS/s, generally fabricated using CMOS process \nwith low to medium resolution ranging from 6 to 12 bits. Even though, these ADCs can \nbe utilized in high-speed electronic measurement devices and radar systems, their latest \nemphasis is driven by the next generation 100 Gbps/500 Gbps fiber optic transceivers. \nThese transceivers use high speed ADCs and DSPs (Digital-Signal-Processors) to \nachieve ultra-fast data communication across long-haul networks (connecting cities, \noceans and continents), metro networks (connecting enterprises within metropolitan \nregions) and data centers (interconnecting infrastructure within data centers). Owing \nto its outstanding power efficiency, the TI SAR ADC has been known as a preferred \nsolution at such high sampling rates. However, this architecture encounters challenges \nassociated with channel mismatches. The three major categories of mismatches include \nan offset mismatch, gain and a timing mismatch. The initial part of this thesis focuses \non developing a MATLAB model to analyze the inherent mismatches found in time \ninterleaved ADCs, which can adversely affect their overall performance. The MATLAB \nmodel plays a vital role for simulating these mismatches, offering valuable \nunderstanding about their effect on the overall functionality of time-interleaved ADCs. \nAs technology evolves and the system requirements become more demanding, the high speed ADCs are constantly pushed to their performance limits. A major challenge in \nADC design encountered in wearable computing machines is that they need ultra-low \npower consumption combined with increasing the sampling rate demands of modern \ncommunication systems. After operational amplifiers, comparators are recognized to be \nthe second most commonly used electronic component and play a significant part in \nADCs by sampling and transforming input signals into digital equivalents. The speed of \nADCs depends on a comparator\u2019s decision-making response time. Ultra-deep \nsubmicron (UDSM) CMOS technology introduces additional complications since \ndevices are required to be operational at lower supply voltages. In contrast, threshold \nvoltages have not scaled down proportionally. As a result, designing high-speed, low \npower and low noise comparators becomes exceptionally problematic, specifically \nunder low voltage conditions. Additionally, a limited common-mode input range occurs \nfrom the low-voltage operation, which is vital for maintaining the effective performance \nof high-speed ADC architectures. As compared to typical comparators, dynamic \ncomparators are remarkably more power-efficient. There are diverse architectures for \ndynamic comparators. The primary focus of this thesis will be the high-speed, low power Strong-Arm Latch comparator for Time-Interleaved SAR ADCs. Initially, the \nStrong-Arm Latch Comparator was simulated (RC Extracted) using 28-nm bulk CMOS \nand was then ported to 22-nm FD-SOI technology. A layout was subsequently carried \nout in this 22-nm FD-SOI technology. An inclusive comparison (RC Extracted) was then \niii\nconducted between these two versions and numerous existing comparators. A Figure of \nMerit (FOM) was computed to facilitate this comparison, and the Strong-Arm Latch \nComparator was evaluated based on its speed, noise and energy per cycle.", "language": "en", "element": "description", "qualifier": "abstract", "schema": "dc"}, {"key": "dc.description.provenance", "value": "Submitted by Paivi Vuorio (paelvuor@jyu.fi) on 2024-09-25T06:21:55Z\nNo. of bitstreams: 0", "language": "en", "element": "description", "qualifier": "provenance", "schema": "dc"}, {"key": "dc.description.provenance", "value": "Made available in DSpace on 2024-09-25T06:21:55Z (GMT). No. of bitstreams: 0\n Previous issue date: 2024", "language": "en", "element": "description", "qualifier": "provenance", "schema": "dc"}, {"key": "dc.format.extent", "value": "68", "language": "", "element": "format", "qualifier": "extent", "schema": "dc"}, {"key": "dc.language.iso", "value": "eng", "language": null, "element": "language", "qualifier": "iso", "schema": "dc"}, {"key": "dc.rights", "value": "In Copyright", "language": "en", "element": "rights", "qualifier": null, "schema": "dc"}, {"key": "dc.title", "value": "Time interleaved SAR ADC", "language": "", "element": "title", "qualifier": null, "schema": "dc"}, {"key": "dc.type", "value": "master thesis", "language": null, "element": "type", "qualifier": null, "schema": "dc"}, {"key": "dc.identifier.urn", "value": "URN:NBN:fi:jyu-202409256076", "language": null, "element": "identifier", "qualifier": "urn", "schema": "dc"}, {"key": "dc.type.ontasot", "value": "Master\u2019s thesis", "language": "en", "element": "type", "qualifier": "ontasot", "schema": "dc"}, {"key": "dc.type.ontasot", "value": "Pro gradu -tutkielma", "language": "fi", "element": "type", "qualifier": "ontasot", "schema": "dc"}, {"key": "dc.contributor.faculty", "value": "Matemaattis-luonnontieteellinen tiedekunta", "language": "fi", "element": "contributor", "qualifier": "faculty", "schema": "dc"}, {"key": "dc.contributor.faculty", "value": "Faculty of Sciences", "language": "en", "element": "contributor", "qualifier": "faculty", "schema": "dc"}, {"key": "dc.contributor.department", "value": "Fysiikan laitos", "language": "fi", "element": "contributor", "qualifier": "department", "schema": "dc"}, {"key": "dc.contributor.department", "value": "Department of Physics", "language": "en", "element": "contributor", "qualifier": "department", "schema": "dc"}, {"key": "dc.contributor.organization", "value": "Jyv\u00e4skyl\u00e4n yliopisto", "language": "fi", "element": "contributor", "qualifier": "organization", "schema": "dc"}, {"key": "dc.contributor.organization", "value": "University of Jyv\u00e4skyl\u00e4", "language": "en", "element": "contributor", "qualifier": "organization", "schema": "dc"}, {"key": "dc.subject.discipline", "value": "Fysiikka", "language": "fi", "element": "subject", "qualifier": "discipline", "schema": "dc"}, {"key": "dc.subject.discipline", "value": "Physics", "language": "en", "element": "subject", "qualifier": "discipline", "schema": "dc"}, {"key": "yvv.contractresearch.funding", "value": "0", "language": "", "element": "contractresearch", "qualifier": "funding", "schema": "yvv"}, {"key": "dc.type.coar", "value": "http://purl.org/coar/resource_type/c_bdcc", "language": null, "element": "type", "qualifier": "coar", "schema": "dc"}, {"key": "dc.rights.accesslevel", "value": "openAccess", "language": null, "element": "rights", "qualifier": "accesslevel", "schema": "dc"}, {"key": "dc.type.publication", "value": "masterThesis", "language": null, "element": "type", "qualifier": "publication", "schema": "dc"}, {"key": "dc.subject.oppiainekoodi", "value": "4021", "language": "", "element": "subject", "qualifier": "oppiainekoodi", "schema": "dc"}, {"key": "dc.rights.url", "value": "https://rightsstatements.org/page/InC/1.0/", "language": null, "element": "rights", "qualifier": "url", "schema": "dc"}]
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