Study of IR-drop induced jitter in high precision timing ASICs

Study of IR-drop induced jitter in high precision timing ASICs

The design, testing and manufacturing of application-specific-integrated circuits (ASICs) have become increasingly complex due to large-scale device integration and advancements in technology scaling. Very-large-scale integration (VLSI) has remarkably enhanced electronic circuit performance, impacti...

Täydet tiedot

Bibliografiset tiedot
Päätekijä: Peninon Herbaut, David
Muut tekijät: Matemaattis-luonnontieteellinen tiedekunta, Faculty of Sciences, Fysiikan laitos, Department of Physics, Jyväskylän yliopisto, University of Jyväskylä
Aineistotyyppi: Pro gradu
Kieli:eng
Julkaistu: 2024
Aiheet:
timing detectors
pixelated detectors and associated VLSI circuits
digital electronic circuits
IR drop
jitter
CERN
Cadence Voltus
Cadence Tempus
TIE jitter
Elektroniikka
Electronics
4022
simulointi
elektroniikka
mikroelektroniikka
simulaattorit
lopukkeet
verifiointi
luotettavuus
simulation
electronics
microelectronics
simulators
cadences
verification
reliability (general)
Linkit: https://jyx.jyu.fi/handle/123456789/97196

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