Design of an analog feature extraction for event-based neuromorphic processor

When climate change becomes more and more prevalent around the world, reducing power consumption of electronic devices, as a result, gets the close attention of the technological research. One of the research fields suggests the neuromorphic processor as one of the possible solutions. The processor...

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Bibliographic Details
Main Author: Tran, Lan
Other Authors: Matemaattis-luonnontieteellinen tiedekunta, Faculty of Sciences, Fysiikan laitos, Department of Physics, Jyväskylän yliopisto, University of Jyväskylä
Format: Master's thesis
Language:eng
Published: 2024
Subjects:
Online Access: https://jyx.jyu.fi/handle/123456789/97143
Description
Summary:When climate change becomes more and more prevalent around the world, reducing power consumption of electronic devices, as a result, gets the close attention of the technological research. One of the research fields suggests the neuromorphic processor as one of the possible solutions. The processor has the potential to overcome the power bottleneck of. the traditional Von Neumann architecture, by emulating the way the human brain processes information every day. It is noticeable that the human brain consumes significantly low power to accomplish complex cognitive tasks, therefore, the brain-like (i.e. neuromorphic) processor is predicted to perform similarly in terms of power consumption. However, the neuromorphic processor does not have the common digital interface as the traditional ones. Consequently, the demand for compatible sensors (such as image, sound, etc.) needs to be satisfied. That is the main topic of this thesis. Developing an auditory analog feature extraction frontend aims to firstly provide a suitable input for the neuromorphic processor, and secondly achieve low power consumption. Resembling the neuromorphic approach, the sound sensor will have the overall architecture mimicking the human cochlea, a biological system preprocessing sound efficiently. However, the complete sound sensor is out of the thesis scope. As a steppingstone for the project, the thesis focuses on proposing a promising low power feature extraction frontend for the sensor. The frontend is made of an array of bandpass filters. The schematic and post-layout performance of one bandpass filter is evaluated in this thesis. The bandpass filter with a center frequency of 2.88 kHz and a quality factor of 2.51 has been designed in a 180nm technology. It consumes around 159 nW of static power