Korkean tarkkuuden TDC-järjestelmän toteuttaminen FPGA:lla - Kuusisto, Eetu (2024)
This thesis examines the design, implementation, and investigation of a Time-to-Digital Converter (TDC) system suitable for detecting fast signals. As a basis for the implementation, the STEMlab 125-14 computation and signal processing card manufactured by Red Pitaya was selected, on which the actual TDC circuitry was formed on the FPGA. A tapped delay line, TDL, was used in TDC to achieve faster than reference clock (350MHz) timings. The performance of the constructed TDC system was primarily researched using signals generated by a signal generator. However, to examine the system in real measurements, a detector suitable for detecting muons was also constructed. The thesis presents the constructed prototype muon detector and its operating principle. Additionally, it briefly introduces the characteristics and formation mechanisms of cosmic muons detectable with the equipment. The focus of the thesis is on signal processing of the detector and the investigation of the TDC system’s performance. Furthermore, measurements were also conducted using LaBr3(Ce) scintillation detectors sensitive to gamma radiation. The obtained results show that the TDC works very well, especially in measurements made using the signal generator. The time resolution of the system was typically < 45 ps. The main research questions of the thesis are the evaluation of the performance of the constructed TDC system in detecting fast signals, as well as its operation and suitability as part of a muon detection system. The TDC system developed for the thesis is intended to be used in the future as part of other detector systems as well.