VAL_AI: an integrated debugger tool for post-silicon validation

As demands for more complex SoCs becomes high due to several technological advancements, the market for these chips is endless and companies are driven to keep up with the changing times by streamlining their top-down process for a more efficient flow. Post-silicon validation is one of the most impo...

Full description

Bibliographic Details
Main Author: Ramos, Cashmere Joy
Other Authors: Matemaattis-luonnontieteellinen tiedekunta, Faculty of Sciences, Fysiikan laitos, Department of Physics, Jyväskylän yliopisto, University of Jyväskylä
Format: Master's thesis
Language:eng
Published: 2023
Subjects:
Online Access: https://jyx.jyu.fi/handle/123456789/89140
_version_ 1828193043457507328
author Ramos, Cashmere Joy
author2 Matemaattis-luonnontieteellinen tiedekunta Faculty of Sciences Fysiikan laitos Department of Physics Jyväskylän yliopisto University of Jyväskylä
author_facet Ramos, Cashmere Joy Matemaattis-luonnontieteellinen tiedekunta Faculty of Sciences Fysiikan laitos Department of Physics Jyväskylän yliopisto University of Jyväskylä Ramos, Cashmere Joy Matemaattis-luonnontieteellinen tiedekunta Faculty of Sciences Fysiikan laitos Department of Physics Jyväskylän yliopisto University of Jyväskylä
author_sort Ramos, Cashmere Joy
datasource_str_mv jyx
description As demands for more complex SoCs becomes high due to several technological advancements, the market for these chips is endless and companies are driven to keep up with the changing times by streamlining their top-down process for a more efficient flow. Post-silicon validation is one of the most important steps during System-on-Chip production process as this happens after fabrication to test functionalities of chips in both nominal conditions and varied process, voltage, and temperature conditions. Post-silicon validation debugging is the last line of defense for all possible attacks and bugs. The process involves rigorous amount of iterative and repeated process of opening several files and comparing data from previous tests. Due to the complicated nature of debugging, there is a need to effectively systematize it and automate the current process of digital validation. Moreover, there are many software tools in the development stages and there is also a need to integrate them altogether. This work first starts with expounding on the current process and tools being used by NXP Semiconductors during post-silicon digital validation. The focus is then driven to automate merging files, visualization of data, and identification of possible causes of failure through a three-step solution: data collection, candidate identification, and problem analysis. The work begins with how the test runs are stored, queried, and shown. Two clustering techniques: kmeans and agglomerative clustering are also discussed. Some dimension reduction techniques like principal component analysis and uniform manifold and approximation projection were also elaborated. These techniques could help development and future work. Application integration is the last step to unify all infant software tools currently in the works under NXP Semiconductors.
first_indexed 2023-09-18T20:01:20Z
format Pro gradu
free_online_boolean 1
fullrecord [{"key": "dc.contributor.author", "value": "Ramos, Cashmere Joy", "language": "", "element": "contributor", "qualifier": "author", "schema": "dc"}, {"key": "dc.date.accessioned", "value": "2023-09-18T05:44:45Z", "language": null, "element": "date", "qualifier": "accessioned", "schema": "dc"}, {"key": "dc.date.available", "value": "2023-09-18T05:44:45Z", "language": null, "element": "date", "qualifier": "available", "schema": "dc"}, {"key": "dc.date.issued", "value": "2023", "language": "", "element": "date", "qualifier": "issued", "schema": "dc"}, {"key": "dc.identifier.uri", "value": "https://jyx.jyu.fi/handle/123456789/89140", "language": null, "element": "identifier", "qualifier": "uri", "schema": "dc"}, {"key": "dc.description.abstract", "value": "As demands for more complex SoCs becomes high due to several technological advancements, the market for these chips is endless and companies are driven to keep up with the changing times by streamlining their top-down process for a more efficient flow. Post-silicon validation is one of the most important steps during System-on-Chip production process as this happens after fabrication to test functionalities of chips in both nominal conditions and varied process, voltage, and temperature conditions. Post-silicon validation debugging is the last line of defense for all possible attacks and bugs. The process involves rigorous amount of iterative and repeated process of opening several files and comparing data from previous tests. Due to the complicated nature of debugging, there is a need to effectively systematize it and automate the current process of digital validation. Moreover, there are many software tools in the development stages and there is also a need to integrate them altogether. This work first starts with expounding on the current process and tools being used by NXP Semiconductors during post-silicon digital validation. The focus is then driven to automate merging files, visualization of data, and identification of possible causes of failure through a three-step solution: data collection, candidate identification, and problem analysis. The work begins with how the test runs are stored, queried, and shown. Two clustering techniques: kmeans and agglomerative clustering are also discussed. Some dimension reduction techniques like principal component analysis and uniform manifold and approximation projection were also elaborated. These techniques could help development and future work. Application integration is the last step to unify all infant software tools currently in the works under NXP Semiconductors.", "language": "en", "element": "description", "qualifier": "abstract", "schema": "dc"}, {"key": "dc.description.provenance", "value": "Submitted by Paivi Vuorio (paelvuor@jyu.fi) on 2023-09-18T05:44:44Z\nNo. of bitstreams: 0", "language": "en", "element": "description", "qualifier": "provenance", "schema": "dc"}, {"key": "dc.description.provenance", "value": "Made available in DSpace on 2023-09-18T05:44:45Z (GMT). No. of bitstreams: 0\n Previous issue date: 2023", "language": "en", "element": "description", "qualifier": "provenance", "schema": "dc"}, {"key": "dc.format.extent", "value": "34", "language": "", "element": "format", "qualifier": "extent", "schema": "dc"}, {"key": "dc.language.iso", "value": "eng", "language": null, "element": "language", "qualifier": "iso", "schema": "dc"}, {"key": "dc.rights", "value": "In Copyright", "language": null, "element": "rights", "qualifier": null, "schema": "dc"}, {"key": "dc.title", "value": "VAL_AI: an integrated debugger tool for post-silicon validation", "language": "", "element": "title", "qualifier": null, "schema": "dc"}, {"key": "dc.type", "value": "master thesis", "language": null, "element": "type", "qualifier": null, "schema": "dc"}, {"key": "dc.identifier.urn", "value": "URN:NBN:fi:jyu-202309185159", "language": "", "element": "identifier", "qualifier": "urn", "schema": "dc"}, {"key": "dc.type.ontasot", "value": "Master\u2019s thesis", "language": "en", "element": "type", "qualifier": "ontasot", "schema": "dc"}, {"key": "dc.type.ontasot", "value": "Pro gradu -tutkielma", "language": "fi", "element": "type", "qualifier": "ontasot", "schema": "dc"}, {"key": "dc.contributor.faculty", "value": "Matemaattis-luonnontieteellinen tiedekunta", "language": "fi", "element": "contributor", "qualifier": "faculty", "schema": "dc"}, {"key": "dc.contributor.faculty", "value": "Faculty of Sciences", "language": "en", "element": "contributor", "qualifier": "faculty", "schema": "dc"}, {"key": "dc.contributor.department", "value": "Fysiikan laitos", "language": "fi", "element": "contributor", "qualifier": "department", "schema": "dc"}, {"key": "dc.contributor.department", "value": "Department of Physics", "language": "en", "element": "contributor", "qualifier": "department", "schema": "dc"}, {"key": "dc.contributor.organization", "value": "Jyv\u00e4skyl\u00e4n yliopisto", "language": "fi", "element": "contributor", "qualifier": "organization", "schema": "dc"}, {"key": "dc.contributor.organization", "value": "University of Jyv\u00e4skyl\u00e4", "language": "en", "element": "contributor", "qualifier": "organization", "schema": "dc"}, {"key": "dc.subject.discipline", "value": "Fysiikka", "language": "fi", "element": "subject", "qualifier": "discipline", "schema": "dc"}, {"key": "dc.subject.discipline", "value": "Physics", "language": "en", "element": "subject", "qualifier": "discipline", "schema": "dc"}, {"key": "yvv.contractresearch.collaborator", "value": "business", "language": "", "element": "contractresearch", "qualifier": "collaborator", "schema": "yvv"}, {"key": "yvv.contractresearch.funding", "value": "0", "language": "", "element": "contractresearch", "qualifier": "funding", "schema": "yvv"}, {"key": "yvv.contractresearch.initiative", "value": "student", "language": "", "element": "contractresearch", "qualifier": "initiative", "schema": "yvv"}, {"key": "dc.type.coar", "value": "http://purl.org/coar/resource_type/c_bdcc", "language": null, "element": "type", "qualifier": "coar", "schema": "dc"}, {"key": "dc.rights.copyright", "value": "\u00a9 The Author(s)", "language": null, "element": "rights", "qualifier": "copyright", "schema": "dc"}, {"key": "dc.rights.accesslevel", "value": "openAccess", "language": null, "element": "rights", "qualifier": "accesslevel", "schema": "dc"}, {"key": "dc.type.publication", "value": "masterThesis", "language": null, "element": "type", "qualifier": "publication", "schema": "dc"}, {"key": "dc.subject.oppiainekoodi", "value": "4021", "language": "", "element": "subject", "qualifier": "oppiainekoodi", "schema": "dc"}, {"key": "dc.subject.yso", "value": "validointi", "language": null, "element": "subject", "qualifier": "yso", "schema": "dc"}, {"key": "dc.subject.yso", "value": "validation", "language": null, "element": "subject", "qualifier": "yso", "schema": "dc"}, {"key": "dc.rights.url", "value": "https://rightsstatements.org/page/InC/1.0/", "language": null, "element": "rights", "qualifier": "url", "schema": "dc"}]
id jyx.123456789_89140
language eng
last_indexed 2025-03-31T20:02:12Z
main_date 2023-01-01T00:00:00Z
main_date_str 2023
online_boolean 1
online_urls_str_mv {"url":"https:\/\/jyx.jyu.fi\/bitstreams\/f3f9a7d1-faf8-4de5-b2ff-bd8922291646\/download","text":"URN:NBN:fi:jyu-202309185159.pdf","source":"jyx","mediaType":"application\/pdf"}
publishDate 2023
record_format qdc
source_str_mv jyx
spellingShingle Ramos, Cashmere Joy VAL_AI: an integrated debugger tool for post-silicon validation Fysiikka Physics 4021 validointi validation
title VAL_AI: an integrated debugger tool for post-silicon validation
title_full VAL_AI: an integrated debugger tool for post-silicon validation
title_fullStr VAL_AI: an integrated debugger tool for post-silicon validation VAL_AI: an integrated debugger tool for post-silicon validation
title_full_unstemmed VAL_AI: an integrated debugger tool for post-silicon validation VAL_AI: an integrated debugger tool for post-silicon validation
title_short VAL_AI: an integrated debugger tool for post-silicon validation
title_sort val ai an integrated debugger tool for post silicon validation
title_txtP VAL_AI: an integrated debugger tool for post-silicon validation
topic Fysiikka Physics 4021 validointi validation
topic_facet 4021 Fysiikka Physics validation validointi
url https://jyx.jyu.fi/handle/123456789/89140 http://www.urn.fi/URN:NBN:fi:jyu-202309185159
work_keys_str_mv AT ramoscashmerejoy valaianintegrateddebuggertoolforpostsiliconvalidation