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locks
study
electronics
history
electronic circuits
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http://www.yso.fi/onto/yso/p5269
http://www.yso.fi/onto/yso/p4781
http://www.yso.fi/onto/yso/p4890
http://www.yso.fi/onto/yso/p1780
http://www.yso.fi/onto/yso/p953
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| author |
Marinaci, Stefano
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| author2 |
Matemaattis-luonnontieteellinen tiedekunta
Faculty of Sciences
Fysiikan laitos
Department of Physics
Jyväskylän yliopisto
University of Jyväskylä
Elektroniikka
Electronics
4022
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Marinaci, Stefano
Matemaattis-luonnontieteellinen tiedekunta
Faculty of Sciences
Fysiikan laitos
Department of Physics
Jyväskylän yliopisto
University of Jyväskylä
Elektroniikka
Electronics
4022
Marinaci, Stefano
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Marinaci, Stefano
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Jyväskylän yliopisto
JYX-julkaisuarkisto
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Marinaci, Stefano
Study of a Phase Locked Loop based Clock and Data Recovery circuit for 2.5 Gbps data-rate
PLL-based CDR
High-speed Link communication systems
low-noise PLL
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Elektroniikka
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https://jyu.finna.fi/Cover/Show?source=Solr&id=jyx.123456789_89109&index=0&size=large
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| title |
Study of a Phase Locked Loop based Clock and Data Recovery circuit for 2.5 Gbps data-rate
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| title_full |
Study of a Phase Locked Loop based Clock and Data Recovery circuit for 2.5 Gbps data-rate
|
| title_fullStr |
Study of a Phase Locked Loop based Clock and Data Recovery circuit for 2.5 Gbps data-rate
Study of a Phase Locked Loop based Clock and Data Recovery circuit for 2.5 Gbps data-rate
|
| title_full_unstemmed |
Study of a Phase Locked Loop based Clock and Data Recovery circuit for 2.5 Gbps data-rate
Study of a Phase Locked Loop based Clock and Data Recovery circuit for 2.5 Gbps data-rate
|
| title_short |
Study of a Phase Locked Loop based Clock and Data Recovery circuit for 2.5 Gbps data-rate
|
| title_sort |
study of a phase locked loop based clock and data recovery circuit for 2 5 gbps data rate
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| title_txtP |
Study of a Phase Locked Loop based Clock and Data Recovery circuit for 2.5 Gbps data-rate
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| topic |
PLL-based CDR
High-speed Link communication systems
low-noise PLL
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| topic_facet |
High-speed Link communication systems
PLL-based CDR
low-noise PLL
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https://jyx.jyu.fi/handle/123456789/89109
http://www.urn.fi/URN:NBN:fi:jyu-202309155130
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AT marinacistefano studyofaphaselockedloopbasedclockanddatarecoverycircuitfor25gbpsdatarate
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