Study of a Phase Locked Loop based Clock and Data Recovery circuit for 2.5 Gbps data-rate

Study of a Phase Locked Loop based Clock and Data Recovery circuit for 2.5 Gbps data-rate

Bibliographic Details
Main Author: Marinaci, Stefano
Other Authors: Matemaattis-luonnontieteellinen tiedekunta, Faculty of Sciences, Fysiikan laitos, Department of Physics, Jyväskylän yliopisto, University of Jyväskylä, Elektroniikka, Electronics, 4022
Format: Master's thesis
Language:eng
Published: 2023
Subjects:
PLL-based CDR
High-speed Link communication systems
low-noise PLL
Online Access: https://jyx.jyu.fi/handle/123456789/89109
Description
Description not available.

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