APA-viite (7. p.)

Marinaci, S., tiedekunta, M., Sciences, F. o., laitos, F., Physics, D. o., yliopisto, J., & Jyväskylä, U. o. (2023). Study of a Phase Locked Loop based Clock and Data Recovery circuit for 2.5 Gbps data-rate.

Chicago-viite (17. p.)

Marinaci, Stefano, Matemaattis-luonnontieteellinen tiedekunta, Faculty of Sciences, Fysiikan laitos, Department of Physics, Jyväskylän yliopisto, ja University of Jyväskylä. Study of a Phase Locked Loop Based Clock and Data Recovery Circuit for 2.5 Gbps Data-rate. 2023.

MLA-viite (9. p.)

Marinaci, Stefano, et al. Study of a Phase Locked Loop Based Clock and Data Recovery Circuit for 2.5 Gbps Data-rate. 2023.