APA (7th ed.) Citation

Marinaci, S., tiedekunta, M., Sciences, F. o., laitos, F., Physics, D. o., yliopisto, J., & Jyväskylä, U. o. (2023). Study of a Phase Locked Loop based Clock and Data Recovery circuit for 2.5 Gbps data-rate.

Chicago Style (17th ed.) Citation

Marinaci, Stefano, Matemaattis-luonnontieteellinen tiedekunta, Faculty of Sciences, Fysiikan laitos, Department of Physics, Jyväskylän yliopisto, and University of Jyväskylä. Study of a Phase Locked Loop Based Clock and Data Recovery Circuit for 2.5 Gbps Data-rate. 2023.

MLA (9th ed.) Citation

Marinaci, Stefano, et al. Study of a Phase Locked Loop Based Clock and Data Recovery Circuit for 2.5 Gbps Data-rate. 2023.