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verification
design (artistic creation)
computer programmes
modelling (representation)
generators (devices)
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http://www.yso.fi/onto/yso/p6609
http://www.yso.fi/onto/yso/p6455
http://www.yso.fi/onto/yso/p26592
http://www.yso.fi/onto/yso/p3533
http://www.yso.fi/onto/yso/p2546
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| author |
Kahale, Theresa
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| author2 |
Matemaattis-luonnontieteellinen tiedekunta
Faculty of Sciences
Fysiikan laitos
Department of Physics
Jyväskylän yliopisto
University of Jyväskylä
Elektroniikka
Electronics
4022
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Kahale, Theresa
Matemaattis-luonnontieteellinen tiedekunta
Faculty of Sciences
Fysiikan laitos
Department of Physics
Jyväskylän yliopisto
University of Jyväskylä
Elektroniikka
Electronics
4022
Kahale, Theresa
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Kahale, Theresa
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Jyväskylän yliopisto
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Kahale, Theresa
Template code generator for design verification based on universal verification methodology
UVM
template code generator
verification environment and testbenches
chip design
verifiointi
mikroelektroniikka
simulointi
verification
microelectronics
simulation
|
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Elektroniikka
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https://jyu.finna.fi/Cover/Show?source=Solr&id=jyx.123456789_89067&index=0&size=large
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Template code generator for design verification based on universal verification methodology
|
| title_full |
Template code generator for design verification based on universal verification methodology
|
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Template code generator for design verification based on universal verification methodology
Template code generator for design verification based on universal verification methodology
|
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Template code generator for design verification based on universal verification methodology
Template code generator for design verification based on universal verification methodology
|
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Template code generator for design verification based on universal verification methodology
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template code generator for design verification based on universal verification methodology
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Template code generator for design verification based on universal verification methodology
|
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UVM
template code generator
verification environment and testbenches
chip design
verifiointi
mikroelektroniikka
simulointi
verification
microelectronics
simulation
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UVM
chip design
microelectronics
mikroelektroniikka
simulation
simulointi
template code generator
verification
verification environment and testbenches
verifiointi
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https://jyx.jyu.fi/handle/123456789/89067
http://www.urn.fi/URN:NBN:fi:jyu-202309145089
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AT kahaletheresa templatecodegeneratorfordesignverificationbasedonuniversalverificationmethodology
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