| Yhteenveto: | In recent years, the semiconductor industry has been showing advanced growth driven by the increasing demand for electronic devices such as smartphones, laptops, tablets and other consumer electronics. Given their extensive applications, the need for higher performance and efficiency requirements has led to smart and innovative development of complex designs, resulting in a more challenging verification process. With the highest workload (around 70%) on verification, adopting tools and methodologies such as Universal Verification Methodology (UVM) is critical to enhance the quality of the design and increase the time-to-market with no defects. UVM is a SystemVerilog based architecture that provides a library to establish robust verification environments. It enables the use of customizable modular and reusable components and testbenches. To reduce the verification time and effort, this master thesis proposes a UVM code generator which instantiates the essential infrastructure for UVM verification components and creates the necessary directory structure for the codes and the files. Given the design input and UVM template files, the code generator will compose the building blocks such as the interfaces and UVM verification components (UVC), environments and testbenches that will connect the Design Under Test (DUT) to the UVCs. The UVM standard structure and proper encapsulation will be adopted to allow for flexible modification and reusability in top level verification environments. To ensure its correct functionality, the tool will be tested on a simple AHB SRAM Controller that manages access to a single port SRAM interface. Constrained random tests will be provided including the necessary checks to get full coverage on the design. Overall, the work on the template code generator enables the automation of block level verification using UVM by providing the verification engineers with the completed testbench and environment to test the DUT.
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